The Switch

Pick up a modern graphics card and the first thing you notice is the weight. An RTX 4090 is over two kilograms of aluminium fins, copper pipes, and three fans. Almost none of that is the computer. The computer is a square of silicon about 2.5 cm on a side, hidden under the middle of the heatsink, and on that square sit 76.3 billion transistors. The rest of the card exists to feed it power and carry away the heat it makes.

Part 2 ended in 1959 with two inventions: a way to print many transistors onto one piece of silicon, and a new kind of transistor, the MOSFET, that switched by electric field rather than by current. Those two are what the 76.3 billion are made of. This part is about the switch itself: how it works, why it can only be on or off, how a chip full of them is actually printed, what "4 nanometres" does and does not mean, why a chip cannot simply be made bigger, and the physical limit that decided, twenty years ago, that the future of computing would be wide rather than fast.

A switch you flip with electricity

A light switch is a gap in a wire. Close the gap with your finger and current flows, open it and the current stops. That is the whole idea of a switch, and it is the most important idea in computing, because a switch has exactly two states and you can tell them apart from a mile away. Parts 1 and 2 showed the two ways of flipping one without a finger that came before the transistor: a magnet moving an arm, and a grid throttling a stream of electrons in a vacuum.

The kind of transistor used in every modern chip is called a MOSFET (metal-oxide-semiconductor field-effect transistor, and you will never need the long form again). It is the triode with the vacuum, the glass, and the heater taken away, and the three parts renamed. It has three terminals. Current wants to flow from the source to the drain, but between them sits a thin strip of silicon that normally does not conduct. Above that strip, separated by an insulating layer only a few atoms thick, sits the gate. Put a voltage on the gate and its electric field pulls charge into the strip underneath, turning it into a conductor. Take the voltage away and the strip goes back to being an insulator. The gate never touches the channel. It flips the switch by influence alone, which is why it is called a field-effect transistor, and it is why the switch can flip billions of times a second with nothing wearing out.

The garden tap from Part 2 carries straight over. The handle is the gate, water enters at the source and leaves at the drain, and turning the handle does not itself move any water, it just opens the path. The analogy breaks in two honest places. First, a tap has a range of positions, whereas we will use the transistor at only two: fully open and fully shut. Second, a tap handle takes a second to turn, while a transistor's gate switches in a few picoseconds, a trillionth of a second. Try it below.

Why two states and not ten

Nothing about a transistor forces you to use only two states. Put a middle voltage on the gate and the channel half-conducts. Early on, some engineers built machines that used several voltage levels per wire, and there are still specialised chips today that do, including the memory in your phone. For a processor, though, two states won out, and the reason is noise.

Every wire in a chip picks up interference from its neighbours, from heat, from the power supply wobbling. If you try to carry the number 7 as "0.7 volts", a little noise turns it into 0.65 and the machine reads 6. If you carry only two values, fully on and fully off, the noise has to be enormous before anyone gets confused, and every transistor cleans the signal up again as it passes through. Two states is not a limitation, it is a design decision that buys reliability. We name the states 0 and 1, call one of them a bit, and from there on the machine counts in twos. Part 4 shows how you add and multiply with nothing but bits and switches, which is the part I found hardest to believe when I first learned it.

From one to 76 billion

The first transistor at Bell Labs was the size of a fingernail, held together with a paperclip and some wax, and for a decade transistors were made and soldered one at a time, which merely moved the tyranny of numbers from the tubes to the joints. The step that made modern computing possible was the one Part 2 ended on: Jack Kilby at Texas Instruments and Robert Noyce at Fairchild independently worked out how to make many transistors, and the wires between them, on a single piece of silicon in one manufacturing process. That is the integrated circuit, and the important word is process. You do not build a chip one transistor at a time. You print it.

How a chip is printed

A chip is made the way a photograph is developed, not the way a house is built. The pattern for a whole layer exists once, on a mask, and light copies it onto the silicon in a single flash. Nothing is placed by hand. Here is one layer, start to finish.

Begin with a wafer, a mirror-polished disc of pure silicon about the size of a dinner plate, and grow or deposit on it a thin film of whatever this layer is made of, a conductor or an insulator. Coat the film with a light-sensitive liquid called photoresist, which changes when light hits it, the way camera film does. Now shine ultraviolet light down through the mask, a quartz plate carrying the pattern for this layer drawn large, and through a lens that shrinks the pattern about fourfold as it lands on the wafer. Where light strikes, the resist is chemically changed. Develop the wafer, and the changed resist washes away, leaving a stencil of hardened resist exactly in the shape of the pattern. Then etch: bathe the wafer in a reactive gas or acid that eats away the film wherever the stencil does not protect it. Strip off the remaining resist, and the film is left shaped. Where transistors need it, a further step called doping fires in the trace impurities from Part 2 that set where the silicon conducts.

That is one layer. A modern chip has sixty to a hundred of them, each printed, developed, etched, and aligned to the one below within a fraction of a transistor's width, and each of the hundreds of chips on the wafer printed at the same instant. The whole run takes months and hundreds of steps, and this is why the process is the product: the machine that does the printing, an extreme-ultraviolet scanner, is the most expensive and precise tool humanity builds, and only a handful of companies on Earth, led by TSMC, can run the most advanced ones at all. It is also why printing a billion transistors costs about the same as printing a thousand. The hard part is making the mask and the machine. Once you have them, the light does not care how intricate the pattern is.

It is worth being clear about what those layers actually are, because "sixty layers" sounds like sixty copies of the same thing and it is not. The bottom few layers build the transistors themselves, printed into the surface of the silicon. Every layer above them is wiring: flat metal tracks that carry signals and power from one transistor to another, stacked ten to fifteen storeys deep because a chip with tens of billions of transistors needs kilometres of wire to connect them and no single flat layer has room. Think of a chip as a building seen edge-on. The transistors are the machinery on the ground floor, each metal layer above is a storey of corridors, and short vertical links called vias are the lifts that join one storey to the next. Signals ride up from a transistor, across a corridor on some floor, and back down to another transistor, and the routes are so dense that the upper floors of a modern chip are given over almost entirely to carrying power in and heat's worth of current around.

Moore's law, and the half everyone forgets

In 1965 Gordon Moore, who would go on to co-found Intel, wrote a four-page article noticing that the number of components the industry could put on a chip had been doubling every year, and guessing it would keep doing so. He was right for longer than anyone had any business expecting: the doubling, later revised to about every two years, held for half a century, and it is the reason the chip in your phone outruns the room-sized machines of the 1960s.

The part that gets dropped from the retelling is that Moore's argument was about cost, not just count. His actual claim was that there is, at any moment, a number of components per chip that makes each component as cheap as possible. Put too few on a chip and you waste the fixed cost of making the chip at all. Cram too many and yield falls, defects bite, and the price per working transistor climbs again. What his law really said is that this cheapest point moves, roughly doubling every couple of years, so each new generation made transistors both more numerous and cheaper. That second half is the one that has faltered. Since around the 28 nm generation, a little over a decade ago, the newest process no longer makes each transistor reliably cheaper, because the machines and masks needed to print finer patterns have grown so costly that they eat the savings. Chips keep gaining transistors. They have stopped getting cheaper per transistor, and that quiet change is behind a lot of what the last third of this series describes. A few points on the count curve:

Two lines in that table look odd next to each other, and untangling them is the next section.

A bigger die, or a denser one?

The AD102 in an RTX 4090 measures 608.5 mm². That number is not a target anyone chose, it is the measured area of the finished die, the silicon rectangle you would see if you pried off the metal lid, and dividing the 76.3 billion transistors by it gives about 125 million transistors per square millimetre. Now look at the Hopper line. The GH100 has more transistors, 80 billion, but its die is much bigger, 814 mm², so its density works out to about 98 million per square millimetre, which is actually lower. Hopper did not pack its transistors tighter. It got more of them the blunt way, by using a bigger piece of silicon, one built right up against the physical ceiling we are about to meet, and a data-centre price tag to match.

Which raises the obvious question: if a bigger die gives you more transistors, why not just keep making the die bigger? Two reasons, and they are the twin walls the rest of this part is about. The first is money, and it comes straight from how printing works. The wafer is a fixed-size disc, and flaws, a stray particle, a tiny misalignment, land on it at random no matter how clean the factory. Cut the wafer into a few big dies and you fit fewer of them, and every single flaw destroys a large, expensive piece. Cut it into many small dies and the same flaws kill only a few tiny ones. So the cost of a die climbs much faster than its area, and past a point it climbs off a cliff.

This is why chipmakers chase density, transistors per square millimetre, rather than simply making dies bigger. A denser die is a cheaper die for the same power, because it fits more of the wafer and loses less to each defect. Making transistors denser is what "a new process node" means, and it is worth being concrete about what shrinking actually is.

What "4 nanometres" means, and what shrinking is

To shrink a transistor is not to make one part smaller. It is to reprint the entire pattern finer: the gate, the channel, the spacing between wires, every dimension scaled down together, historically by about 0.7 each generation, which packs roughly twice as many transistors into the same area. A shorter channel also switches faster and holds less charge, so for decades a shrink delivered three gifts at once, more transistors, more speed, less energy each. That triple gift is the engine that drove the whole industry, and later in this part we will see it break.

Which brings us to the names. You will see Ada and Hopper described as "4 nm" chips, and Blackwell as "4NP". A nanometre is a billionth of a metre. A human hair is about 80,000 nm across, a virus is around 100 nm, and the spacing between atoms in silicon is about 0.5 nm. So "4 nm" sounds like a physical measurement, and it once was: the node name used to be the length of the transistor's gate. It is not any more. Around the 22 nm generation, in about 2012, the names came unstuck from any physical dimension and turned into marketing labels for successive generations of manufacturing, each a bit denser than the last but none of them actually four, or twenty-two, nanometres of anything. TSMC's "4N", the process Nvidia uses for Ada and Hopper, is a tuned version of TSMC's 5 nm-class family, and the TechInsights editorial Nanometer Nonsense is a good read on how little the number now tells you. What is real is the density it delivers, and the hard ceiling that density runs into.

The reticle limit, and why it sits where it does

The second wall is not about money. It is about optics, and it does not move. Look again at the printing step: the pattern for one chip is projected, through a lens, onto one rectangle of the wafer. That rectangle, the exposure field, is as large as the lens can sharply project, and on today's machines that is about 26 mm by 33 mm, which is 858 mm². The pattern for a single chip has to fit inside it. This ceiling is the reticle limit, and the name is worth unpacking, because it is where the section title comes from: reticle is the industry's word for the mask, the patterned plate the light shines through, so the reticle limit is simply the largest mask image the machine can project in one exposure. When a spec sheet calls a die "reticle-sized", this 858 mm² is the reticle it means. Hopper's 814 mm² die sits just under the line, which is no accident: it is as large as a chip can be.

Why can the machine not simply project a bigger field? Because the lens is already at the edge of what physics and manufacturing allow. It weighs as much as a small car, is ground and polished to a smoothness measured in fractions of an atom, and focuses light with a wavelength smaller than a virus. Widening its field would demand a larger lens held to the same impossible tolerance, and a larger mask held to the same tolerance too, and both the cost and the flaw rate rise faster than any customer can bear. So 858 mm² is not a number that improves with the next generation. It is a wall.

There is exactly one way past a wall like that: stop trying to make one die bigger, and instead print two or more separate dies and wire them together so tightly that the software cannot tell. That is precisely what Blackwell did with two dies, what Rubin does with two, and what Rubin Ultra will do with four. The question "how many dies per package" did not exist as a headline five years ago. It is now one of the first numbers on the spec sheet, and it exists because of this wall.

"Wire them together" hides most of the difficulty. Two dies sitting a hair's breadth apart are still two separate chips, and for the software to treat them as one, a signal crossing from one die to the other has to arrive almost as quickly and as cheaply as a signal that stayed home. Ordinary circuit-board wiring is far too slow for that, so the dies are joined by a dense bridge, a patch carrying thousands of tiny wires packed into the narrow strip where the dies meet. Blackwell's version moves 10 terabytes a second across that seam, more than the bandwidth to the chip's own memory, which is what lets the two halves pretend to be one. The hard parts are exactly the ones you would expect once you picture it: the link has to run at nearly the speed of wiring inside a single die or the illusion breaks, it has to fit thousands of connections into a sliver of space aligned to within microns, and it burns extra power and throws off extra heat right at the join, which is already one of the hottest places on the chip. Part 16 opens Blackwell's version up in detail.

Speed, and the price of speed

Every time a gate flips, it has to be charged up or drained, and that costs a tiny amount of energy. Tiny, but a modern chip flips billions of gates a few billion times a second. Multiply it out and you get the 450 W that an RTX 4090 draws under load, and the heatsink that outweighs the chip a thousand times over.

For decades the heat stayed manageable because of a happy accident of physics called Dennard scaling, described by Robert Dennard and colleagues at IBM in a 1974 paper. A chip's switching power follows a simple rule: it is proportional to the size of each switch, times the square of the voltage it runs at, times how often it flips per second. Because voltage enters as a square, it is by far the strongest lever. And every time transistors shrank, they could run at a lower voltage, so the square term fell sharply, which left room to raise the clock speed for free without adding heat. Smaller, faster, and no hotter, generation after generation.

Around 2005 the lever jammed, and the reason is the two currents every transistor carries. One is the switching current, the useful pulse when the gate deliberately opens or closes the channel. The other is leakage, a thin trickle that flows through the transistor even when it is meant to be fully off. To turn a transistor cleanly off, its gate voltage has to swing below a threshold, and as voltages were pushed lower and lower, that threshold got too close to the floor: drop the voltage any further and the transistor never quite shuts, so leakage swells until the chip pours out heat while doing nothing at all.

So the voltage could not keep falling, the square term stopped shrinking, and the free lunch ended. With voltage stuck, raising the clock speed no longer came for free: by the power rule, doubling the clock now roughly doubles the power, and all of it as heat. The Pentium 4 hit 3.8 GHz in 2004, and twenty years later consumer chips are still in the 5 GHz range, because that is about as fast as you can flip a switch without cooking the silicon around it.

This one fact reshaped the industry. If you cannot make one switch flip faster, the only way to do more work is to have more switches flipping at once. CPUs went from one core to a handful. GPUs, as we will see in Part 7, took that idea to the extreme, and the end of Dennard scaling is the reason their design bet paid off.

Where this leaves us

A graphics processor is 76 billion switches, each flipped by an electric field rather than a finger, printed onto a square of silicon by light, and cooled by two kilograms of metal. Every one of those switches can only be on or off. There is nothing else in there. No numbers, no pictures, no neural network, just switches and the wires between them.

Everything from here on is about the arrangement. A few dozen switches, arranged one way, add two numbers. A few thousand multiply them. Wrap those in some memory and a clock and you have a processor. Copy that processor thousands of times, give the copies a clever way to share work, and you have a GPU. Put 72 of those in a rack and you have the machine that trains a language model. Same switch all the way up. Next, we arrange a handful of them to do the first half of w × x + b.

Next: From Switches to Sums: how switches become logic gates, how gates add and multiply, and why a multiplier that uses fewer bits is smaller, faster, and cooler, which turns out to be the whole plot of modern AI hardware.